Shrouk S.

Aspiring Digital IC Design Engineer with a solid foundation in digital logic, electronic systems, and signal processing. Skilled in Verilog and VHDL for RTL design, with hands-on experience in implementing and simulating projects on FPGA platforms using tools like Vivado, Quartus, ModelSim, and QuestaSim. Currently learning the ASIC design flow, including synthesis, timing analysis, and verification. Known for strong problem-solving abilities, fast learning, and a commitment to applying academic knowledge to practical hardware design challenges. Actively seeking industry collaboration or sponsorship to support my graduation project and contribute to innovative IC design solutions. Projects UART (Universal Asynchronous Receiver Transmitter) Design Verilog | ModelSim Asynchronous FIFO Design VHDL | ModelSim | Vivado INST_RISC Processor Core Verilog | ModelSim Online Courses & Certifications Full ASIC Flow Diploma — Instructor: Eng. Ali ElTemsah (Present) Digital IC Design on FPGA using VHDL & Verilog — National Telecommunication Institute (NTI), 2025