Ahmed T.

I'm Ahmed Tarek, a dedicated Electronics and Communications Engineering student at Ain Shams

University with a growing passion for Digital IC Design. My focus lies in digital systems, RTL design,

and FPGA. I have hands-on experience with Verilog, SystemVerilog, Static Timing Analysis (STA),

and Clock Domain Crossing (CDC) techniques.

I’ve developed and implemented core digital design components like UART, SPI protocols, RISC-V

cores, and DSP module targeting Spartan-6 FPGAs. My toolchain includes Vivado and QuestaSim,

and I’m continually expanding my expertise in Digital design and verification.