Mano Basic Computer Implementation in Verilog & Proteus

Mano Basic Computer Implementation in Verilog & Proteus

Designed and implemented Mano’s Basic Computer architecture with the complete 16-bit instruction set, using Verilog HDL for digital logic and Proteus for hardware simulation.

Key Features & Contributions:

Implemented full Memory Reference, Register Reference, and I/O instructions as defined in Mano’s model.

Developed modular Verilog components: ALU, Control Unit (FSM), Memory, Registers (with E flag), and dedicated I/O module.

Added stack operations (PUSH/POP), interrupt handling (ION/IOF), and conditional branching instructions.

Created extended Proteus simulations with test programs for arithmetic, I/O, and stack operations.

Verified design functionality via waveform analysis and functional test cases.

Technologies:

Verilog HDL, Proteus, FSM Design, Digital Logic Design, Computer Architecture.

Impact:

Demonstrates a complete, simulation-ready educational CPU model that bridges theoretical computer architecture concepts with practical HDL implementation—ideal for teaching, research, and FPGA prototyping.Mano Basic Computer Implementation in Verilog & Proteus Designed and implemented Mano’s Basic Computer architecture with the complete 16-bit instruction set, using Verilog HDL for digital logic and Proteus for hardware simulation. Key Features & Contributions: Implemented full Memory Reference, Register Reference, and I/O instructions as defined in Mano’s model. Developed modular Verilog components: ALU, Control Unit (FSM), Memory, Registers (with E flag), and dedicated I/O module. Added stack operations (PUSH/POP), interrupt handling (ION/IOF), and conditional branching instructions. Created extended Proteus simulations with test programs for arithmetic, I/O, and stack operations. Verified design functionality via waveform analysis and functional test cases. Technologies: Verilog HDL, Proteus, FSM Design, Digital Logic Design, Computer Architecture. Impact: Demonstrates a complete, simulation-ready educational CPU model that bridges theoretical computer architecture concepts with practical HDL implementation—ideal for teaching, research, and FPGA prototyping.

Skills: Field-Programmable Gate Arrays (FPGA) · Computer Hardware · Computer Simulations · Computer-Aided Design (CAD) · Program Management · FPGA · Computer Maintenance · Logic Design · Logic Programming