Adjustable 24-Hour Digital Clock Circuit (CMOS 4026 & 555 Timer)

Note: This project was developed as a collaborative academic team effort by Zaid Hatem Khalil El-Sharkawy and team. My primary contribution focused on circuit simulation, logic testing, and hands-on breadboard hardware implementation. Designed, simulated, and prototyped a fully hardware-based 24-hour digital clock without using any microcontrollers, demonstrating core digital logic design, clock generation, and sequential circuit synchronization. System Architecture & Key Engineering Details:Clock Pulse Generation: Implemented a 555 timer configured in Astable mode to produce a stable square-wave clock signal. Included a frequency-adjusting circuit to accelerate time pulses during manual setting. Synchronous Counting & Display Stages: Cascaded six CD4026 CMOS decade counter/divider ICs to directly drive common-cathode 7-segment displays: Seconds & Minutes Stages: Modulo-60 counters (00–59). Hours Stage: Modulo-24 counter (00–23) with custom reset detection. Diode Logic Gate Implementation: Built custom 3-input AND gates using 1N4148 diodes and pull-up resistors to handle Mod-60 and Mod-24 reset conditions, avoiding unnecessary gate IC footprint and minimizing signal crossing. Manual Time Calibration: Integrated SPDT switches to allow switching between normal clock pulses and fast-calibration pulses for adjusting hours and minutes independently, with a halt toggle for seconds. Simulation & Breadboard Prototyping: Validated the complete schematic on Proteus, followed by a clean 3-tier breadboard build optimized to isolate electromagnetic interference (EMI) and maintain signal integrity across CMOS lines. Core Components & Tools: CD4026B Counter/Decoder ICs, NE555 Timer, 1N4148 Diodes, Seven-Segment Displays, SPDT Switches, Proteus Design Suite.