4*1 Multiplexer Design

This project focuses on the design and analysis of a digital logic block using CMOS

technology. The objective is to design a 4×1 multiplexer (MUX) at the transistor level using

the TSMC 65 nm technology in Cadence Virtuoso. The project includes schematic design,

layout implementation, and post-layout verification to ensure correct functionality and

compliance with design rules.