full adder

In this project, I successfully designed and implemented the layout of a Full Adder circuit using Cadence Virtuoso. The Full Adder is a fundamental combinational circuit that performs binary addition of three inputs (

?

A,

?

B, and

?

?

?

C

in

) to produce two outputs: Sum (

?

S) and Carry (

?

?

?

?

C

out

).

The design utilized:

2 XOR gates to calculate the Sum output (

?

=

?

⊕

?

⊕

?

?

?

S=A⊕B⊕C

in

),

2 AND gates and 1 OR gate to compute the Carry output (

?

?

?

?

=

?

⋅

?

+

?

?

?

⋅

(

?

⊕

?

)

C

out

=A⋅B+C

in

⋅(A⊕B)).

The workflow included:

Schematic Design: I created the circuit schematic for the Full Adder to define its logical functionality.

Layout Design: Using Cadence Virtuoso, I implemented the physical layout for each gate (AND, XOR, OR) and integrated them into a compact Full Adder layout while adhering to design rules (DRC).

Routing and Power Distribution: Proper routing techniques and power distribution (VDD and GND rails) were applied to ensure efficient interconnectivity.

Verification: The layout was verified against the schematic using Layout vs. Schematic (LVS) checks to ensure accuracy and consistency between the schematic and physical design.