MIPS VHDL

Project Description: MIPS Processor Design in VHDL

This project involves the design and implementation of a MIPS (Microprocessor without Interlocked Pipeline Stages) processor using VHDL. The primary goal is to create a functional MIPS processor that supports a subset of the MIPS instruction set, demonstrating fundamental concepts of computer architecture.

Key Features:

Architecture: Implements a single-cycle or multi-cycle MIPS processor.

Instruction Set: Supports basic instructions, including arithmetic (ADD, SUB), logical (AND, OR), memory access (LW, SW), and control flow (BEQ, JUMP).

Modules:

Instruction Fetch (IF): Fetches instructions from memory.

Instruction Decode (ID): Decodes the fetched instruction and reads registers.

Execution (EX): Performs arithmetic and logical operations.

Memory Access (MEM): Handles data transfer between memory and processor.

Write Back (WB): Writes results back to registers.

Data Path: Includes components such as ALU, register file, program counter (PC), memory unit, and control unit.

Control Unit: Generates control signals based on instruction type.

Simulation and Testing: The design is simulated using a testbench to verify functionality against known test cases.

Tools and Technologies:

Language: VHDL

Simulation and Synthesis: Performed using tools such as ModelSim.